Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.

<!--HTML-->The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This co...

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Autor principal: Bergamin, Gianmario
Lenguaje:eng
Publicado: 2021
Materias:
Conferences
Acceso en línea:http://cds.cern.ch/record/2781958
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author Bergamin, Gianmario
author_facet Bergamin, Gianmario
author_sort Bergamin, Gianmario
collection CERN
description <!--HTML-->The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that show limited coverage and long testing time. Scan-chain design, memory and Logic Built-In-Self-Test have been adapted for radiation-hard ASICs and introduced on-chip for a novel testing approach. Design flow and implementation choices will be presented together with silicon results.
id cern-2781958
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2021
record_format invenio
spelling cern-27819582022-11-02T22:02:15Zhttp://cds.cern.ch/record/2781958engBergamin, GianmarioImplementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.TWEPP 2021 Topical Workshop on Electronics for Particle PhysicsConferences<!--HTML-->The development of the MPA and SSA ASICs is approaching the production phase with a volume of more than 1000 wafers. The importance of yield management in the construction of the Outer Tracker modules requires rigorous testing methods capable to identify all defective parts. This contribution presents customized Design for Testability methods to replace the currently used functional tests that show limited coverage and long testing time. Scan-chain design, memory and Logic Built-In-Self-Test have been adapted for radiation-hard ASICs and introduced on-chip for a novel testing approach. Design flow and implementation choices will be presented together with silicon results.oai:cds.cern.ch:27819582021
spellingShingle Conferences
Bergamin, Gianmario
Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.
title Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.
title_full Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.
title_fullStr Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.
title_full_unstemmed Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.
title_short Implementation and testing of Design For Testability methodologies in 65 nm ASICs for HL-LHC.
title_sort implementation and testing of design for testability methodologies in 65 nm asics for hl-lhc.
topic Conferences
url http://cds.cern.ch/record/2781958
work_keys_str_mv AT bergamingianmario implementationandtestingofdesignfortestabilitymethodologiesin65nmasicsforhllhc
AT bergamingianmario twepp2021topicalworkshoponelectronicsforparticlephysics

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