Cargando…

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to SingleEvent Effects (SE...

Descripción completa

Detalles Bibliográficos
Autores principales:	Biereigel, Stefan, Kulis, Szymon, Moreira, Paulo, Kölpin, Alexander, Leroux, Paul, Prinzie, Jeffrey
Lenguaje:	eng
Publicado:	2021
Materias:	Detectors and Experimental Techniques Nuclear Physics - Experiment
Acceso en línea:	https://dx.doi.org/10.3390/electronics10222741 http://cds.cern.ch/record/2807905

Ejemplares similares

Single-Event Effect Responses of Integrated Planar Inductors in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2021)

Radiation-Tolerant Digitally Controlled Ring Oscillator in 65-nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2022)

The lpGBT PLL and CDR Architecture, Performance and SEE Robustness
por: Biereigel, Stefan, et al.
Publicado: (2020)

Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS
por: Biereigel, Stefan, et al.
Publicado: (2019)

Radiation hard true single-phase-clock logic for high-speed circuits in 28 nm CMOS
por: Klekotko, A, et al.
Publicado: (2023)

A High-resolution, Wide-range, Radiation-hard Clock Phase-shifter in a 65 nm CMOS Technology
por: Kulis, Szymon, et al.
Publicado: (2019)

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology
por: Prinzie, Jeffrey, et al.
Publicado: (2017)

A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit with High Speed Feed Forward Correction in 65 nm CMOS
por: Prinzie, Jeffrey, et al.
Publicado: (2019)

Study of SEU Sensitivity of SRAM-Based Radiation Monitors in 65-nm CMOS
por: Wang, Jialei, et al.
Publicado: (2021)

A High-Resolution Clock Phase-Shifter in a 65 nm CMOS Technology
por: Yang, Dongxu, et al.
Publicado: (2018)

A Compact Low-Power Driver Array for VCSELs in 65-nm CMOS Technology
por: Zeng, Zhiyao, et al.
Publicado: (2017)

Methods for clock signal characterization using FPGA resources
por: Biereigel, S, et al.
Publicado: (2020)

Source Switched Charge-Pump PLLs for High-Dose Radiation Environments
por: Prinzie, Jeffrey, et al.
Publicado: (2023)

CMOS 65nm engineering run
por: Re, Valerio
Publicado: (2018)

CMOS PLL Synthesizers: Analysis and Design
por: Shu, Keliu, et al.
Publicado: (2005)

Radiation-tolerant all-digital clock generators for HEP applications
por: Biereigel, S, et al.
Publicado: (2023)

A radiation-hard PLL for frequency multiplication with programmable input clock and phase-selectable output signals in 130 nm CMOS
por: Poltorak, K, et al.
Publicado: (2012)

Developments of two 4 × 10 Gb/s VCSEL array drivers in 65 nm CMOS for HEP experiments
por: Guo, D, et al.
Publicado: (2017)

Final design review of 65nm CMOS chips
por: Re, Valerio
Publicado: (2017)

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS
por: Kruth, A, et al.
Publicado: (2009)

Pixel front-end development in 65 nm CMOS technology
por: Havránek, M, et al.
Publicado: (2014)

The eCDR, a Radiation-Hard 40/80/160/320 Mbit/s CDR with internal VCO frequency calibration and 195 ps programmable phase resolution in 130 nm CMOS
por: Tavernier, Filip, et al.
Publicado: (2013)

The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
por: Leitao, P, et al.
Publicado: (2015)

CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology
por: Muñoz-Gamarra, Jose Luis, et al.
Publicado: (2016)

Characterization of a commercial 65 nm CMOS technology for SLHC applications
por: Bonacini, S, et al.
Publicado: (2012)

Optimization of a 65 nm CMOS imaging process for monolithic CMOS sensors for high energy physics
por: Rinella, G Aglieri, et al.
Publicado: (2023)

QTIA, a 2.5 or 10 Gbps 4-channel array optical receiver ASIC in a 65 nm CMOS technology
por: Sun, H., et al.
Publicado: (2021)

65 nm CMOS analog front-end for pixel detectors at the HL-LHC
por: Gaioni, L, et al.
Publicado: (2016)

Digital Pixel Test Structures implemented in a 65 nm CMOS process
por: Rinella, Gianluca Aglieri, et al.
Publicado: (2022)

Perspectives of 65 nm CMOS technologies for high performance front-end electronics
por: Traversi, G, et al.
Publicado: (2014)

Effects of Bias and Temperature on the Dose-Rate Sensitivity of 65-nm CMOS Transistors
por: Borghello, Giulio, et al.
Publicado: (2021)

Radiation hardened CMOS integrated circuits for time-based signal processing
por: Prinzie, Jeffrey, et al.
Publicado: (2018)

Charge sensing properties of monolithic CMOS pixel sensors fabricated in a 65 nm technology
por: Bugiel, Szymon, et al.
Publicado: (2022)

Impact of clipping noise on the sum rate of NOMA with PD-DCO-OFDM and conventional DCO-OFDM
por: Gebeyehu, Zelalem Hailu
Publicado: (2020)

Dose-Rate Sensitivity of 65-nm MOSFETs Exposed to Ultrahigh Doses
por: Borghello, Giulio, et al.
Publicado: (2018)

A 4-fJ/Spike Artificial Neuron in 65 nm CMOS Technology
por: Sourikopoulos, Ilias, et al.
Publicado: (2017)

Low-Cutoff Frequency Reduction in Neural Amplifiers: Analysis and Implementation in CMOS 65 nm
por: Hashemi Noshahr, Fereidoon, et al.
Publicado: (2021)

Final Report of WP2 DCO
por: Chaudron, M, et al.
Publicado: (2013)

Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS
por: Chevas, Loukas, et al.
Publicado: (2018)

Cannot write session to /tmp/vufind_sessions/sess_lrp7qs1h930qpa5icobluo1mkn