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Configuration Memory Scrubbing of SRAM-Based FPGAs Using a Mixed 2-D Coding Technique
SRAM-based field-programmable gate array (FPGA) vendors typically integrate error correction codes (ECCs) into the configuration memory to assist designers in implementing scrubbing mechanisms. In most cases, these ECC schemes guarantee the correction of single- and double-bit errors per configurati...
| Autores principales: | , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2022
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1109/TNS.2022.3151977 http://cds.cern.ch/record/2807909 |