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Hardware Design and Testing of the Generic Rear Transition Module for the Global Trigger Subsystem of ATLAS Phase-II Upgrade
In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 $\mu s$-latency architecture. The Global Trigger is a new subsystem which will bring event-f...
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| Lenguaje: | eng |
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2022
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| Acceso en línea: | http://cds.cern.ch/record/2840779 |