Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver

A Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitt...

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Detalles Bibliográficos
Autores principales: Bandi, F, Ballabriga, R, Borghello, G, Campbell, M, Caratelli, A, Ceresa, D, Hofmann, T, Kaplon, J, Kloukinas, K, Michelis, S, Pejašinović, R, Piernas-Díaz, F, Piller, M, Traversi, G
Lenguaje:eng
Publicado: 2023
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/18/01/C01039
http://cds.cern.ch/record/2847608

Internet

https://dx.doi.org/10.1088/1748-0221/18/01/C01039
http://cds.cern.ch/record/2847608

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