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Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver

A Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitt...

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Detalles Bibliográficos
Autores principales: Bandi, F, Ballabriga, R, Borghello, G, Campbell, M, Caratelli, A, Ceresa, D, Hofmann, T, Kaplon, J, Kloukinas, K, Michelis, S, Pejašinović, R, Piernas-Díaz, F, Piller, M, Traversi, G
Lenguaje:eng
Publicado: 2023
Materias:
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/18/01/C01039
http://cds.cern.ch/record/2847608
_version_ 1780976805148098560
author Bandi, F
Ballabriga, R
Borghello, G
Campbell, M
Caratelli, A
Ceresa, D
Hofmann, T
Kaplon, J
Kloukinas, K
Michelis, S
Pejašinović, R
Piernas-Díaz, F
Piller, M
Traversi, G
author_facet Bandi, F
Ballabriga, R
Borghello, G
Campbell, M
Caratelli, A
Ceresa, D
Hofmann, T
Kaplon, J
Kloukinas, K
Michelis, S
Pejašinović, R
Piernas-Díaz, F
Piller, M
Traversi, G
author_sort Bandi, F
collection CERN
description A Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitter’s output is powered with 1.2 V to provide compatibility with previous designs, while the core logic can be powered with 0.8 V to reduce power consumption. This work summarizes the design approach at the schematic and layout level. Practical aspects of the novel technology for the design of ASICs in High Energy Physics will be discussed along with characterization results. Other IP blocks are being designed (ADC, DAC, PLL) and they will be presented.
id cern-2847608
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2023
record_format invenio
spelling cern-28476082023-01-26T23:07:09Zdoi:10.1088/1748-0221/18/01/C01039http://cds.cern.ch/record/2847608engBandi, FBallabriga, RBorghello, GCampbell, MCaratelli, ACeresa, DHofmann, TKaplon, JKloukinas, KMichelis, SPejašinović, RPiernas-Díaz, FPiller, MTraversi, GAnalog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiverDetectors and Experimental TechniquesA Scalable Low Voltage Signaling (SLVS) transmitter and receiver have been developed as IP blocks in a 28 nm standard CMOS technology for the future upgrades for the high luminosity LHC. At the target data rate of 1.28 Gbps, the transmitter consumes 6 mW and the receiver consumes 2 mW. The transmitter’s output is powered with 1.2 V to provide compatibility with previous designs, while the core logic can be powered with 0.8 V to reduce power consumption. This work summarizes the design approach at the schematic and layout level. Practical aspects of the novel technology for the design of ASICs in High Energy Physics will be discussed along with characterization results. Other IP blocks are being designed (ADC, DAC, PLL) and they will be presented.oai:cds.cern.ch:28476082023
spellingShingle Detectors and Experimental Techniques
Bandi, F
Ballabriga, R
Borghello, G
Campbell, M
Caratelli, A
Ceresa, D
Hofmann, T
Kaplon, J
Kloukinas, K
Michelis, S
Pejašinović, R
Piernas-Díaz, F
Piller, M
Traversi, G
Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver
title Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver
title_full Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver
title_fullStr Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver
title_full_unstemmed Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver
title_short Analog IP blocks in 28 nm CMOS for the high energy physics community: SLVS transmitter and receiver
title_sort analog ip blocks in 28 nm cmos for the high energy physics community: slvs transmitter and receiver
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/18/01/C01039
http://cds.cern.ch/record/2847608
work_keys_str_mv AT bandif analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT ballabrigar analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT borghellog analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT campbellm analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT caratellia analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT ceresad analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT hofmannt analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT kaplonj analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT kloukinask analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT micheliss analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT pejasinovicr analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT piernasdiazf analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT pillerm analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver
AT traversig analogipblocksin28nmcmosforthehighenergyphysicscommunityslvstransmitterandreceiver