An FPGA-based readout chip emulator for the CMS ETL detector upgrade

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented...

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Detalles Bibliográficos
Autores principales: Zhang, L., Edwards, C., Gong, D., Huang, X., Lee, J., Liu, C., Liu, T., Olsen, J., Sun, Q., Wu, J., Ye, J., Zhang, W.
Lenguaje:eng
Publicado: 2023
Materias:
physics.ins-det
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/18/02/C02031
http://cds.cern.ch/record/2861311

Internet

https://dx.doi.org/10.1088/1748-0221/18/02/C02031
http://cds.cern.ch/record/2861311

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