An FPGA-based readout chip emulator for the CMS ETL detector upgrade

We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented...

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Detalles Bibliográficos
Autores principales: Zhang, L., Edwards, C., Gong, D., Huang, X., Lee, J., Liu, C., Liu, T., Olsen, J., Sun, Q., Wu, J., Ye, J., Zhang, W.
Lenguaje:eng
Publicado: 2023
Materias:
physics.ins-det
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/18/02/C02031
http://cds.cern.ch/record/2861311
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author Zhang, L.
Edwards, C.
Gong, D.
Huang, X.
Lee, J.
Liu, C.
Liu, T.
Olsen, J.
Sun, Q.
Wu, J.
Ye, J.
Zhang, W.
author_facet Zhang, L.
Edwards, C.
Gong, D.
Huang, X.
Lee, J.
Liu, C.
Liu, T.
Olsen, J.
Sun, Q.
Wu, J.
Ye, J.
Zhang, W.
author_sort Zhang, L.
collection CERN
description We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.
id cern-2861311
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2023
record_format invenio
spelling cern-28613112023-06-15T12:14:19Zdoi:10.1088/1748-0221/18/02/C02031doi:10.1088/1748-0221/18/02/C02031http://cds.cern.ch/record/2861311engZhang, L.Edwards, C.Gong, D.Huang, X.Lee, J.Liu, C.Liu, T.Olsen, J.Sun, Q.Wu, J.Ye, J.Zhang, W.An FPGA-based readout chip emulator for the CMS ETL detector upgradephysics.ins-detDetectors and Experimental TechniquesWe present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.We present an FPGA-based readout chip emulator board for the CMS Endcap Timing Layer (ETL) detector upgrade. The emulator board uses an Intel Cyclone 10 GX FPGA to emulate the digital functions of four Endcap Layer Readout Chips (ETROCs). Based on the actual ETROC design, the firmware is implemented and verified. The emulator board is being used for the ETROC digital design verification and system development.arXiv:2302.01548FERMILAB-PUB-23-056-PPDoai:cds.cern.ch:28613112023-02-02
spellingShingle physics.ins-det
Detectors and Experimental Techniques
Zhang, L.
Edwards, C.
Gong, D.
Huang, X.
Lee, J.
Liu, C.
Liu, T.
Olsen, J.
Sun, Q.
Wu, J.
Ye, J.
Zhang, W.
An FPGA-based readout chip emulator for the CMS ETL detector upgrade
title An FPGA-based readout chip emulator for the CMS ETL detector upgrade
title_full An FPGA-based readout chip emulator for the CMS ETL detector upgrade
title_fullStr An FPGA-based readout chip emulator for the CMS ETL detector upgrade
title_full_unstemmed An FPGA-based readout chip emulator for the CMS ETL detector upgrade
title_short An FPGA-based readout chip emulator for the CMS ETL detector upgrade
title_sort fpga-based readout chip emulator for the cms etl detector upgrade
topic physics.ins-det
Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/18/02/C02031
https://dx.doi.org/10.1088/1748-0221/18/02/C02031
http://cds.cern.ch/record/2861311
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