Cargando…
Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate
Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in communication systems for High-Energy Physics (HEP) since are used to generate a high-quality clock signal that maintains synchronicity between the electronic systems. The CDR topology proposed in this thesis can...
Autor principal: | |
---|---|
Lenguaje: | eng |
Publicado: |
2023
|
Materias: | |
Acceso en línea: | http://cds.cern.ch/record/2870334 |