Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate

Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in communication systems for High-Energy Physics (HEP) since are used to generate a high-quality clock signal that maintains synchronicity between the electronic systems. The CDR topology proposed in this thesis can be used to support the development of ASIC that finds application in high-speed link communication systems in the clock distribution system of the High Luminosity Large Hadron Collider (HL-LHC) detectors at CERN. The thesis results from a study based on a theoretical analysis supported by simulations. This proposed work aims to describe the operation of a PLL-based CDR through a highlevel behavioural analysis in Verilog. Advanced analyses are performed by using the Cadence Simulation Platform for modelling the system and Python scripting for requirement definition and post-processing of the data. The dependency of the phase noise and jitter of the PLL is a topic that is relevant in systems designed for high-frequency synthesis, and the analysis of the jitter behaviour is required to minimize the noise contribution. During the design phase, each architectural choice comes with pros and cons, therefore high-level considerations are derived from this study. Different sources of noise are introduced and the effects on the CDR operation are studied to minimize the jitter contribution coming from the reference data stream and from the Digital Control Oscillator (DCO). Furthermore, three CDR topologies that differ from the implementation logic of the downsampler connected at the output of the phase detector are compared. The comparison is done in terms of architectural complexity, bandwidth, jitter, and time to lock. As a result of the study, it is possible to conclude that a different implementation of downsampler logic generates a different phase detector gain in the feedback system, changing the dynamics of the system and its behaviour both in the time and frequency domains. However, it is possible to compensate for the variation of the phase detector gain by selecting different parameters for the digital filter, making in principle the behaviour of the three solutions equivalent. Keywords: PLL-based CDR, High-speed Link communication systems, low-noise PLL.