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Study of a Phase Locked Loop based Clock and Data Recovery Circuit for 2.5 Gbps data-rate
Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) circuits play a big role in communication systems for High-Energy Physics (HEP) since are used to generate a high-quality clock signal that maintains synchronicity between the electronic systems. The CDR topology proposed in this thesis can...
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| Lenguaje: | eng |
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2023
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| Acceso en línea: | http://cds.cern.ch/record/2870334 |