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A blocked implementation of level 3 BLAS for RISC processors
Autores principales: | , |
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Lenguaje: | eng |
Publicado: |
1996
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Materias: | |
Acceso en línea: | http://cds.cern.ch/record/298944 |
_version_ | 1780889317522014208 |
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author | Daydé, M J Duff, I S |
author_facet | Daydé, M J Duff, I S |
author_sort | Daydé, M J |
collection | CERN |
id | cern-298944 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 1996 |
record_format | invenio |
spelling | cern-2989442019-09-30T06:29:59Zhttp://cds.cern.ch/record/298944engDaydé, M JDuff, I SA blocked implementation of level 3 BLAS for RISC processorsComputing and ComputersRAL-TR-96-014oai:cds.cern.ch:2989441996 |
spellingShingle | Computing and Computers Daydé, M J Duff, I S A blocked implementation of level 3 BLAS for RISC processors |
title | A blocked implementation of level 3 BLAS for RISC processors |
title_full | A blocked implementation of level 3 BLAS for RISC processors |
title_fullStr | A blocked implementation of level 3 BLAS for RISC processors |
title_full_unstemmed | A blocked implementation of level 3 BLAS for RISC processors |
title_short | A blocked implementation of level 3 BLAS for RISC processors |
title_sort | blocked implementation of level 3 blas for risc processors |
topic | Computing and Computers |
url | http://cds.cern.ch/record/298944 |
work_keys_str_mv | AT daydemj ablockedimplementationoflevel3blasforriscprocessors AT duffis ablockedimplementationoflevel3blasforriscprocessors AT daydemj blockedimplementationoflevel3blasforriscprocessors AT duffis blockedimplementationoflevel3blasforriscprocessors |