A high-resolution time interpolator based on a delay locked loop and an RC delay line

An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7- mu m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of t...

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Detalles Bibliográficos
Autores principales: Mota, M, Christiansen, J
Lenguaje:eng
Publicado: 1999
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/4.792603
http://cds.cern.ch/record/410824
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author Mota, M
Christiansen, J
author_facet Mota, M
Christiansen, J
author_sort Mota, M
collection CERN
description An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7- mu m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low- power, high-resolution time interpolation circuit in a standard digital CMOS technology. (11 refs).
id cern-410824
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1999
record_format invenio
spelling cern-4108242019-09-30T06:29:59Zdoi:10.1109/4.792603http://cds.cern.ch/record/410824engMota, MChristiansen, JA high-resolution time interpolator based on a delay locked loop and an RC delay lineDetectors and Experimental TechniquesAn architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7- mu m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of the RC delay line is performed using code density tests (CDT). The very small temperature/voltage dependence of R and C parameters and the self calibrating DLL results in a low- power, high-resolution time interpolation circuit in a standard digital CMOS technology. (11 refs).oai:cds.cern.ch:4108241999
spellingShingle Detectors and Experimental Techniques
Mota, M
Christiansen, J
A high-resolution time interpolator based on a delay locked loop and an RC delay line
title A high-resolution time interpolator based on a delay locked loop and an RC delay line
title_full A high-resolution time interpolator based on a delay locked loop and an RC delay line
title_fullStr A high-resolution time interpolator based on a delay locked loop and an RC delay line
title_full_unstemmed A high-resolution time interpolator based on a delay locked loop and an RC delay line
title_short A high-resolution time interpolator based on a delay locked loop and an RC delay line
title_sort high-resolution time interpolator based on a delay locked loop and an rc delay line
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1109/4.792603
http://cds.cern.ch/record/410824
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