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A high-resolution time interpolator based on a delay locked loop and an RC delay line
An architecture for a time interpolation circuit with an rms error of ~25 ps has been developed in a 0.7- mu m CMOS technology. It is based on a delay locked loop (DLL) driven by a 160-MHz reference clock and a passive RC delay line controlled by an autocalibration circuit. Start-up calibration of t...
| Autores principales: | , |
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| Lenguaje: | eng |
| Publicado: |
1999
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| Acceso en línea: | https://dx.doi.org/10.1109/4.792603 http://cds.cern.ch/record/410824 |