Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments

After having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 mu m CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction...

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Detalles Bibliográficos
Autores principales: Anelli, G, Faccio, F, Florian, S, Jarron, Pierre
Lenguaje:eng
Publicado: 2001
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/S0168-9002(00)00761-0
http://cds.cern.ch/record/503755
_version_ 1780897304178327552
author Anelli, G
Faccio, F
Florian, S
Jarron, Pierre
author_facet Anelli, G
Faccio, F
Florian, S
Jarron, Pierre
author_sort Anelli, G
collection CERN
description After having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 mu m CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction at CERN). The 1/f and white noise are studied for n- and p-channel devices with five different gate lengths, in weak, moderate and strong inversion and for different drain to source and bulk to source biases. The noise degradation is measured after irradiation with 10 keV X-rays and after annealing. The results are commented in view of the use of these transistors in low-noise front-end circuits. (22 refs).
id cern-503755
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2001
record_format invenio
spelling cern-5037552019-09-30T06:29:59Zdoi:10.1016/S0168-9002(00)00761-0http://cds.cern.ch/record/503755engAnelli, GFaccio, FFlorian, SJarron, PierreNoise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experimentsDetectors and Experimental TechniquesAfter having reviewed the main noise sources in an MOS transistor the paper presents results about the noise performance of a 0.25 mu m CMOS technology which is being extensively used to design radiation tolerant ASICs for the LHC experiments (the Large Hadron Collider at present under construction at CERN). The 1/f and white noise are studied for n- and p-channel devices with five different gate lengths, in weak, moderate and strong inversion and for different drain to source and bulk to source biases. The noise degradation is measured after irradiation with 10 keV X-rays and after annealing. The results are commented in view of the use of these transistors in low-noise front-end circuits. (22 refs).oai:cds.cern.ch:5037552001
spellingShingle Detectors and Experimental Techniques
Anelli, G
Faccio, F
Florian, S
Jarron, Pierre
Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments
title Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments
title_full Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments
title_fullStr Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments
title_full_unstemmed Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments
title_short Noise characterization of a 0.25 $\mu$ m CMOS technology for the LHC experiments
title_sort noise characterization of a 0.25 $\mu$ m cmos technology for the lhc experiments
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1016/S0168-9002(00)00761-0
http://cds.cern.ch/record/503755
work_keys_str_mv AT anellig noisecharacterizationofa025mumcmostechnologyforthelhcexperiments
AT facciof noisecharacterizationofa025mumcmostechnologyforthelhcexperiments
AT florians noisecharacterizationofa025mumcmostechnologyforthelhcexperiments
AT jarronpierre noisecharacterizationofa025mumcmostechnologyforthelhcexperiments

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