Readout Logic and Its Hardware Implementation in the DIRAC Experiment

Readout logic and architecture of the readout hardware of the experiment DIRAC at CERN are described. The data collection system is configured from dedicated and commercial readout branches running in a parallel hardware-controlled mode. Readout process is controlled by trigger processors which may...

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Detalles Bibliográficos
Autores principales: Karpukhin, V V, Kulikov, A V, Olshevsky, V G, Trusov, S V
Lenguaje:eng
Publicado: 2003
Materias:
Computing and Computers
Acceso en línea:http://cds.cern.ch/record/621739
Descripción
Sumario:Readout logic and architecture of the readout hardware of the experiment DIRAC at CERN are described. The data collection system is configured from dedicated and commercial readout branches running in a parallel hardware-controlled mode. Readout process is controlled by trigger processors which may decide to reject an event during its acquisition. The system design provides a small dead time resulting in a sufficiently high rate capability.

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