An alternative architecture of the L0(æ) processor

97-024 An alternative architecture of the L0(µ) processor and its implementation are presented. The architecture of the processor is based on a strong zero­suppression in order to minimize the data flow coming from the muon detector. It can be achieved by the fast identification of the muon tracks...

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Detalles Bibliográficos
Autores principales: Aslanides, Elie, Dinkespiler, B, Le Gac, R, Menouni, M, Potheau, R
Lenguaje:eng
Publicado: 1997
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/684484
_version_ 1780901456137682944
author Aslanides, Elie
Dinkespiler, B
Le Gac, R
Menouni, M
Potheau, R
author_facet Aslanides, Elie
Dinkespiler, B
Le Gac, R
Menouni, M
Potheau, R
author_sort Aslanides, Elie
collection CERN
description 97-024 An alternative architecture of the L0(µ) processor and its implementation are presented. The architecture of the processor is based on a strong zero­suppression in order to minimize the data flow coming from the muon detector. It can be achieved by the fast identification of the muon tracks in all muon chambers using adequately dimensioned pad sectors and by transferring the individual pad information only for the regions close to the muon tracks. The proposed solution is simple, flexible and compact. Based on present technology the processor could execute the complete L0(µ) algorithm and make its decision available within less than 3 µs.
id cern-684484
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1997
record_format invenio
spelling cern-6844842019-09-30T06:29:59Zhttp://cds.cern.ch/record/684484engAslanides, ElieDinkespiler, BLe Gac, RMenouni, MPotheau, RAn alternative architecture of the L0(æ) processorDetectors and Experimental Techniques97-024 An alternative architecture of the L0(µ) processor and its implementation are presented. The architecture of the processor is based on a strong zero­suppression in order to minimize the data flow coming from the muon detector. It can be achieved by the fast identification of the muon tracks in all muon chambers using adequately dimensioned pad sectors and by transferring the individual pad information only for the regions close to the muon tracks. The proposed solution is simple, flexible and compact. Based on present technology the processor could execute the complete L0(µ) algorithm and make its decision available within less than 3 µs.LHCb-97-024oai:cds.cern.ch:6844841997-12-19
spellingShingle Detectors and Experimental Techniques
Aslanides, Elie
Dinkespiler, B
Le Gac, R
Menouni, M
Potheau, R
An alternative architecture of the L0(æ) processor
title An alternative architecture of the L0(æ) processor
title_full An alternative architecture of the L0(æ) processor
title_fullStr An alternative architecture of the L0(æ) processor
title_full_unstemmed An alternative architecture of the L0(æ) processor
title_short An alternative architecture of the L0(æ) processor
title_sort alternative architecture of the l0(æ) processor
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/684484
work_keys_str_mv AT aslanideselie analternativearchitectureofthel0æprocessor
AT dinkespilerb analternativearchitectureofthel0æprocessor
AT legacr analternativearchitectureofthel0æprocessor
AT menounim analternativearchitectureofthel0æprocessor
AT potheaur analternativearchitectureofthel0æprocessor
AT aslanideselie alternativearchitectureofthel0æprocessor
AT dinkespilerb alternativearchitectureofthel0æprocessor
AT legacr alternativearchitectureofthel0æprocessor
AT menounim alternativearchitectureofthel0æprocessor
AT potheaur alternativearchitectureofthel0æprocessor

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