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Vertex trigger implementation using shared memory technology
The implementation of a 1 st level vertex trigger for LHC-B is particularly difficult due to the high ( 1 MHz ) input data rate. With ca. 350 silicon hits per event, both the R strips and Phi strips of the detectors produce a total of ca 2 Gbyte/s zero-suppressed da ta.1 note succeeds to the ideas t...
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| Lenguaje: | eng |
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1998
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| Acceso en línea: | http://cds.cern.ch/record/691665 |