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Digital signal processors in the LHCb level-1 vertex trigger system
99-002 The note discusses the use of Analog Devices' SHARC Digital Signal Processors for the Level-1 Vertex Trigger system implementation. It presents a short overview of current and future Analog Devices' floating-point DSP architectures, multiprocessor system architectures and a survey o...
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| Lenguaje: | eng |
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1999
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| Acceso en línea: | http://cds.cern.ch/record/691677 |