Digital signal processors in the LHCb level-1 vertex trigger system

99-002 The note discusses the use of Analog Devices' SHARC Digital Signal Processors for the Level-1 Vertex Trigger system implementation. It presents a short overview of current and future Analog Devices' floating-point DSP architectures, multiprocessor system architectures and a survey of available standard DSP board-level components and software for multiprocessor applications. A possible solution for mapping the vertex trigger algorithm on the scaleable DSP multiprocessor is discussed with analysis of its implementation using standard DSP multiprocessor components.