Digital signal processors in the LHCb level-1 vertex trigger system

99-002 The note discusses the use of Analog Devices' SHARC Digital Signal Processors for the Level-1 Vertex Trigger system implementation. It presents a short overview of current and future Analog Devices' floating-point DSP architectures, multiprocessor system architectures and a survey o...

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Detalles Bibliográficos
Autor principal: Bouianov, O
Lenguaje:eng
Publicado: 1999
Materias:
Detectors and Experimental Techniques
Acceso en línea:http://cds.cern.ch/record/691677
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author Bouianov, O
author_facet Bouianov, O
author_sort Bouianov, O
collection CERN
description 99-002 The note discusses the use of Analog Devices' SHARC Digital Signal Processors for the Level-1 Vertex Trigger system implementation. It presents a short overview of current and future Analog Devices' floating-point DSP architectures, multiprocessor system architectures and a survey of available standard DSP board-level components and software for multiprocessor applications. A possible solution for mapping the vertex trigger algorithm on the scaleable DSP multiprocessor is discussed with analysis of its implementation using standard DSP multiprocessor components.
id cern-691677
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 1999
record_format invenio
spelling cern-6916772019-09-30T06:29:59Zhttp://cds.cern.ch/record/691677engBouianov, ODigital signal processors in the LHCb level-1 vertex trigger systemDetectors and Experimental Techniques99-002 The note discusses the use of Analog Devices' SHARC Digital Signal Processors for the Level-1 Vertex Trigger system implementation. It presents a short overview of current and future Analog Devices' floating-point DSP architectures, multiprocessor system architectures and a survey of available standard DSP board-level components and software for multiprocessor applications. A possible solution for mapping the vertex trigger algorithm on the scaleable DSP multiprocessor is discussed with analysis of its implementation using standard DSP multiprocessor components.LHCb-99-002oai:cds.cern.ch:6916771999-01-02
spellingShingle Detectors and Experimental Techniques
Bouianov, O
Digital signal processors in the LHCb level-1 vertex trigger system
title Digital signal processors in the LHCb level-1 vertex trigger system
title_full Digital signal processors in the LHCb level-1 vertex trigger system
title_fullStr Digital signal processors in the LHCb level-1 vertex trigger system
title_full_unstemmed Digital signal processors in the LHCb level-1 vertex trigger system
title_short Digital signal processors in the LHCb level-1 vertex trigger system
title_sort digital signal processors in the lhcb level-1 vertex trigger system
topic Detectors and Experimental Techniques
url http://cds.cern.ch/record/691677
work_keys_str_mv AT bouianovo digitalsignalprocessorsinthelhcblevel1vertextriggersystem

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