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Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
This paper explains the design and the realization of a digital Rad- Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 mum CMOS 3- metal Rad-Hard CERN librar...
| Autores principales: | , , |
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| Lenguaje: | eng |
| Publicado: |
2003
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1016/j.nima.2003.08.090 http://cds.cern.ch/record/808021 |