Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system

This paper explains the design and the realization of a digital Rad- Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 mum CMOS 3- metal Rad-Hard CERN librar...

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Detalles Bibliográficos
Autores principales: Falchieri, D, Gabrielli, A, Gandolfi, E
Lenguaje:eng
Publicado: 2003
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/j.nima.2003.08.090
http://cds.cern.ch/record/808021
Descripción
Sumario:This paper explains the design and the realization of a digital Rad- Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 mum CMOS 3- metal Rad-Hard CERN library. It is composed of 10 kgates, 84 I/O pads out of the 100 total pads, it is clocked at 40MHz, it is pad-limited and the whole die area is 4 multiplied by 4mm **2. The chip has been tested over 20 packaged samples and it has been proved that 12 out of 20 chips work well.

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