Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system

This paper explains the design and the realization of a digital Rad- Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 mum CMOS 3- metal Rad-Hard CERN librar...

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Detalles Bibliográficos
Autores principales: Falchieri, D, Gabrielli, A, Gandolfi, E
Lenguaje:eng
Publicado: 2003
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1016/j.nima.2003.08.090
http://cds.cern.ch/record/808021
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author Falchieri, D
Gabrielli, A
Gandolfi, E
author_facet Falchieri, D
Gabrielli, A
Gandolfi, E
author_sort Falchieri, D
collection CERN
description This paper explains the design and the realization of a digital Rad- Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 mum CMOS 3- metal Rad-Hard CERN library. It is composed of 10 kgates, 84 I/O pads out of the 100 total pads, it is clocked at 40MHz, it is pad-limited and the whole die area is 4 multiplied by 4mm **2. The chip has been tested over 20 packaged samples and it has been proved that 12 out of 20 chips work well.
id cern-808021
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2003
record_format invenio
spelling cern-8080212019-09-30T06:29:59Zdoi:10.1016/j.nima.2003.08.090http://cds.cern.ch/record/808021engFalchieri, DGabrielli, AGandolfi, EDesign and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition systemDetectors and Experimental TechniquesThis paper explains the design and the realization of a digital Rad- Hard chip. The design is a part of the Large Hadron Collider (LHC), A Large Ion Collider Experiment (ALICE) at CERN. The chip has been designed in VHDL-Verilog language and implemented in 0.25 mum CMOS 3- metal Rad-Hard CERN library. It is composed of 10 kgates, 84 I/O pads out of the 100 total pads, it is clocked at 40MHz, it is pad-limited and the whole die area is 4 multiplied by 4mm **2. The chip has been tested over 20 packaged samples and it has been proved that 12 out of 20 chips work well.oai:cds.cern.ch:8080212003
spellingShingle Detectors and Experimental Techniques
Falchieri, D
Gabrielli, A
Gandolfi, E
Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
title Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
title_full Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
title_fullStr Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
title_full_unstemmed Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
title_short Design and fabrication of a 025 mum Rad-Hard ASIC for ALICE ITS data acquisition system
title_sort design and fabrication of a 025 mum rad-hard asic for alice its data acquisition system
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1016/j.nima.2003.08.090
http://cds.cern.ch/record/808021
work_keys_str_mv AT falchierid designandfabricationofa025mumradhardasicforaliceitsdataacquisitionsystem
AT gabriellia designandfabricationofa025mumradhardasicforaliceitsdataacquisitionsystem
AT gandolfie designandfabricationofa025mumradhardasicforaliceitsdataacquisitionsystem

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