The new LHCb trigger and DAQ strategy: a system architecture based on gigabit-ethernet

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The LHCb software trigger has two levels: a high-speed trigger running at 1 MHz with strictly limited latency and a second level running below 40 kHz without latency limitations. The trigger strategy requires full flexibility in the distribution of the installed CPU power to the two software trigger...

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Detalles Bibliográficos
Autores principales: Barczyk, A, Dufey, J P, Gaspar, C, Gavillet, P, Jacobsson, R, Jost, B, Neufeld, N, Vannerem, P
Lenguaje:eng
Publicado: 2004
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/TNS.2004.828600
http://cds.cern.ch/record/816767

Internet

https://dx.doi.org/10.1109/TNS.2004.828600
http://cds.cern.ch/record/816767

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