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A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments
A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-mum CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-Omega line driver, internal self-testing...
Autores principales: | , , |
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Lenguaje: | eng |
Publicado: |
2004
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1109/TNS.2004.829551 http://cds.cern.ch/record/816802 |
_version_ | 1780905440300761088 |
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author | Cervelli, Giovanni Marchioro, Alessandro Moreira, Paulo |
author_facet | Cervelli, Giovanni Marchioro, Alessandro Moreira, Paulo |
author_sort | Cervelli, Giovanni |
collection | CERN |
description | A 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-mum CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-Omega line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds. 13 Refs. |
id | cern-816802 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2004 |
record_format | invenio |
spelling | cern-8168022019-09-30T06:29:59Zdoi:10.1109/TNS.2004.829551http://cds.cern.ch/record/816802engCervelli, GiovanniMarchioro, AlessandroMoreira, PauloA 013-mum CMOS serializer for data and trigger optical links in particle physics experimentsDetectors and Experimental TechniquesA 3.2-Gbit/s serializer prototype has been fabricated in a 0.13-mum CMOS technology to demonstrate its applicability within future Large Hadron Collider (LHC) data readout and trigger systems. The IC includes a clock-multiplying phase-locked-loop (PLL), a 50-Omega line driver, internal self-testing features, and data pattern generation. The serial output stream is 8 B/10 B encoded for compatibility with commercial receivers. Radiation hardening layout techniques have been adopted, which guarantee radiation tolerant operation inside the innermost LHC detectors over more than 10 yr. This paper describes the circuit architecture and reports on the experimental results. Signal quality (jitter, noise floor, eye opening) and bit-error rate (BER) are measured at different transmission rates using laboratory instrumentation and dedicated test beds. 13 Refs.oai:cds.cern.ch:8168022004 |
spellingShingle | Detectors and Experimental Techniques Cervelli, Giovanni Marchioro, Alessandro Moreira, Paulo A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments |
title | A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments |
title_full | A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments |
title_fullStr | A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments |
title_full_unstemmed | A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments |
title_short | A 013-mum CMOS serializer for data and trigger optical links in particle physics experiments |
title_sort | 013-mum cmos serializer for data and trigger optical links in particle physics experiments |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.1109/TNS.2004.829551 http://cds.cern.ch/record/816802 |
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