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BDC 500 branch driver controller
This processor has been designed for very fast data acquisition and date pre-processing. The dataway and branch highway speeds have been optimized for approximately 1.5 mu sec. The internal processor cycle is approximately 0.8 mu sec. The standard version contains the following functions (slots): cr...
| Autores principales: | , |
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| Lenguaje: | eng |
| Publicado: |
CERN
1981
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.5170/CERN-1981-007.418 http://cds.cern.ch/record/878044 |