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An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology
A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 \mum by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication...
Autores principales: | , , , , , , , , , , |
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Lenguaje: | eng |
Publicado: |
2005
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Materias: | |
Acceso en línea: | https://dx.doi.org/10.1016/j.nima.2005.11.065 http://cds.cern.ch/record/893063 |
_version_ | 1780908569857622016 |
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author | Chefdeville, M Colas, P Giomataris, Ioanis van der Graaf, H Heijne, Erik H M Van der Putten, S Salm, C Schmitz, J Smits, S Timmermans, J Visschers, J L |
author_facet | Chefdeville, M Colas, P Giomataris, Ioanis van der Graaf, H Heijne, Erik H M Van der Putten, S Salm, C Schmitz, J Smits, S Timmermans, J Visschers, J L |
author_sort | Chefdeville, M |
collection | CERN |
description | A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 \mum by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication occurs : primary electrons from the drift space above the grid enter the holes and cause electron avalanches in the high-field region between the grid and the anode. Production and operational characteristics of the device are described. With this newly developed technology, CMOS (pixel) readout chips can be covered with a gas multiplication grid. Such a chip forms, together with the grid, an integrated device which can be applied as readout in a wide field of gaseous detectors. |
id | cern-893063 |
institution | Organización Europea para la Investigación Nuclear |
language | eng |
publishDate | 2005 |
record_format | invenio |
spelling | cern-8930632019-09-30T06:29:59Zdoi:10.1016/j.nima.2005.11.065http://cds.cern.ch/record/893063engChefdeville, MColas, PGiomataris, Ioanisvan der Graaf, HHeijne, Erik H MVan der Putten, SSalm, CSchmitz, JSmits, STimmermans, JVisschers, J LAn electron-multiplying "Micromegas" grid made in silicon wafer post-processing technologyDetectors and Experimental TechniquesA technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 \mum by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication occurs : primary electrons from the drift space above the grid enter the holes and cause electron avalanches in the high-field region between the grid and the anode. Production and operational characteristics of the device are described. With this newly developed technology, CMOS (pixel) readout chips can be covered with a gas multiplication grid. Such a chip forms, together with the grid, an integrated device which can be applied as readout in a wide field of gaseous detectors.CERN-PH-EP-2005-042DAPNIA-2005-210NIKHEF-2005-017oai:cds.cern.ch:8930632005-09-20 |
spellingShingle | Detectors and Experimental Techniques Chefdeville, M Colas, P Giomataris, Ioanis van der Graaf, H Heijne, Erik H M Van der Putten, S Salm, C Schmitz, J Smits, S Timmermans, J Visschers, J L An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology |
title | An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology |
title_full | An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology |
title_fullStr | An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology |
title_full_unstemmed | An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology |
title_short | An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology |
title_sort | electron-multiplying "micromegas" grid made in silicon wafer post-processing technology |
topic | Detectors and Experimental Techniques |
url | https://dx.doi.org/10.1016/j.nima.2005.11.065 http://cds.cern.ch/record/893063 |
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