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FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in...
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| Lenguaje: | eng |
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2004
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| Acceso en línea: | https://dx.doi.org/10.1117/12.568878 http://cds.cern.ch/record/908972 |