FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in...

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Detalles Bibliográficos
Autor principal: Pozniak, Krzysztof T
Lenguaje:eng
Publicado: 2004
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1117/12.568878
http://cds.cern.ch/record/908972
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author Pozniak, Krzysztof T
author_facet Pozniak, Krzysztof T
author_sort Pozniak, Krzysztof T
collection CERN
description The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.
id cern-908972
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2004
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spelling cern-9089722019-09-30T06:29:59Zdoi:10.1117/12.568878http://cds.cern.ch/record/908972engPozniak, Krzysztof TFPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experimentsDetectors and Experimental TechniquesThe paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.oai:cds.cern.ch:9089722004
spellingShingle Detectors and Experimental Techniques
Pozniak, Krzysztof T
FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
title FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
title_full FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
title_fullStr FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
title_full_unstemmed FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
title_short FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments
title_sort fpga-based fast pipeline-parameterized-sorter implementation for first level trigger systems in hep experiments
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1117/12.568878
http://cds.cern.ch/record/908972
work_keys_str_mv AT pozniakkrzysztoft fpgabasedfastpipelineparameterizedsorterimplementationforfirstleveltriggersystemsinhepexperiments

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