Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment

Lowest level (sometimes called Level 0, L0) triggers are fundamental components in high energy physics experiments, and yet they are quite often custom-made. Even when using FPGAs to achieve better flexibility in modifying and maintaining, small changes require hardware reconfiguration and changes t...

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Detalles Bibliográficos
Autores principales: Pivanti, M, Schifano, S F, Dalpiaz, P, Gamberini, E, Gianoli, A, Sozzi, M
Lenguaje:eng
Publicado: 2014
Materias:
Detectors and Experimental Techniques
Computing and Computers
Acceso en línea:https://dx.doi.org/10.1088/1742-6596/513/1/012008
http://cds.cern.ch/record/2026294
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author Pivanti, M
Schifano, S F
Dalpiaz, P
Gamberini, E
Gianoli, A
Sozzi, M
author_facet Pivanti, M
Schifano, S F
Dalpiaz, P
Gamberini, E
Gianoli, A
Sozzi, M
author_sort Pivanti, M
collection CERN
description Lowest level (sometimes called Level 0, L0) triggers are fundamental components in high energy physics experiments, and yet they are quite often custom-made. Even when using FPGAs to achieve better flexibility in modifying and maintaining, small changes require hardware reconfiguration and changes to the algorithm logic could be constrained by the hardware. For these reasons we are developing for the NA62 experiment at CERN a L0-trigger based on the use of a PC and commodity FPGA development board.
id oai-inspirehep.net-1301908
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2014
record_format invenio
spelling oai-inspirehep.net-13019082022-08-17T13:29:04Zdoi:10.1088/1742-6596/513/1/012008http://cds.cern.ch/record/2026294engPivanti, MSchifano, S FDalpiaz, PGamberini, EGianoli, ASozzi, MImplementation of a PC-based Level 0 Trigger Processor for the NA62 ExperimentDetectors and Experimental TechniquesComputing and ComputersLowest level (sometimes called Level 0, L0) triggers are fundamental components in high energy physics experiments, and yet they are quite often custom-made. Even when using FPGAs to achieve better flexibility in modifying and maintaining, small changes require hardware reconfiguration and changes to the algorithm logic could be constrained by the hardware. For these reasons we are developing for the NA62 experiment at CERN a L0-trigger based on the use of a PC and commodity FPGA development board.oai:inspirehep.net:13019082014
spellingShingle Detectors and Experimental Techniques
Computing and Computers
Pivanti, M
Schifano, S F
Dalpiaz, P
Gamberini, E
Gianoli, A
Sozzi, M
Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
title Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
title_full Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
title_fullStr Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
title_full_unstemmed Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
title_short Implementation of a PC-based Level 0 Trigger Processor for the NA62 Experiment
title_sort implementation of a pc-based level 0 trigger processor for the na62 experiment
topic Detectors and Experimental Techniques
Computing and Computers
url https://dx.doi.org/10.1088/1742-6596/513/1/012008
http://cds.cern.ch/record/2026294
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AT schifanosf implementationofapcbasedlevel0triggerprocessorforthena62experiment
AT dalpiazp implementationofapcbasedlevel0triggerprocessorforthena62experiment
AT gamberinie implementationofapcbasedlevel0triggerprocessorforthena62experiment
AT gianolia implementationofapcbasedlevel0triggerprocessorforthena62experiment
AT sozzim implementationofapcbasedlevel0triggerprocessorforthena62experiment

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