Development of a 4 GS/s Intra-bunch Instability Control System for the SPS - Next Steps

We present the expanded system architecture in development for the control of intra-bunch instabilities in the SPS. Earlier efforts concentrated on validating the performance of a single-bunch demonstration processor. This minimal system was successfully commissioned at the SPS just prior to the LS1...

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Detalles Bibliográficos
Autores principales: Fox, John, Cesaratto, John, Dusatko, John, Pollock, Kristin, Rivetta, Claudio, Turgut, Ozhan, De Santis, Stefano, Höfle, Wolfgang, Kotzian, Gerd, Wehrle, Urs
Lenguaje:eng
Publicado: 2014
Materias:
Accelerators and Storage Rings
Acceso en línea:http://cds.cern.ch/record/2003139

Internet

http://cds.cern.ch/record/2003139

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