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Development of a low power 5.12 Gbps data serializer and wireline transmitter circuit for the VeloPix chip
A new front-end chip (VeloPix) is being developed for the readout of the silicon vertex locator detector (VELO) in the LHCb experiment after the upgrade scheduled for 2018. The chip with an active area of 2 cm(2) will run at a very high hit rate (up to 500 Mhitcm(−)(2)sec(−)(1)) and will transmit la...
| Autores principales: | , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2015
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/10/01/C01054 http://cds.cern.ch/record/2158928 |