Low-power clock distribution circuits for the Macro Pixel ASIC

Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the HL-LHC. This work reviews different CMOS circuit architectur...

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Detalles Bibliográficos
Autores principales: Gaioni, L, De Canio, F, Manghisoni, M, Ratti, L, Re, V, Traversi, G, Marchioro, A, Kloukinas, K
Lenguaje:eng
Publicado: 2015
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/10/01/C01051
http://cds.cern.ch/record/2158930
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author Gaioni, L
De Canio, F
Manghisoni, M
Ratti, L
Re, V
Traversi, G
Marchioro, A
Kloukinas, K
author_facet Gaioni, L
De Canio, F
Manghisoni, M
Ratti, L
Re, V
Traversi, G
Marchioro, A
Kloukinas, K
author_sort Gaioni, L
collection CERN
description Clock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed, based on standard supply voltage and on auxiliary, reduced supply. Circuit performance, in terms of power consumption and speed, is evaluated for each of the proposed solutions and compared with that relevant to standard CMOS drivers.
id oai-inspirehep.net-1342713
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2015
record_format invenio
spelling oai-inspirehep.net-13427132019-09-30T06:29:59Zdoi:10.1088/1748-0221/10/01/C01051http://cds.cern.ch/record/2158930engGaioni, LDe Canio, FManghisoni, MRatti, LRe, VTraversi, GMarchioro, AKloukinas, KLow-power clock distribution circuits for the Macro Pixel ASICDetectors and Experimental TechniquesClock distribution circuits account for a significant fraction of the power dissipation of the Macro Pixel ASIC (MPA), designed for the pixel layer readout of the so-called Pixel-Strip module in the innermost part of the CMS tracker at the HL-LHC. This work reviews different CMOS circuit architectures envisioned for low power clock distribution in the MPA. Two main topologies will be discussed, based on standard supply voltage and on auxiliary, reduced supply. Circuit performance, in terms of power consumption and speed, is evaluated for each of the proposed solutions and compared with that relevant to standard CMOS drivers.oai:inspirehep.net:13427132015
spellingShingle Detectors and Experimental Techniques
Gaioni, L
De Canio, F
Manghisoni, M
Ratti, L
Re, V
Traversi, G
Marchioro, A
Kloukinas, K
Low-power clock distribution circuits for the Macro Pixel ASIC
title Low-power clock distribution circuits for the Macro Pixel ASIC
title_full Low-power clock distribution circuits for the Macro Pixel ASIC
title_fullStr Low-power clock distribution circuits for the Macro Pixel ASIC
title_full_unstemmed Low-power clock distribution circuits for the Macro Pixel ASIC
title_short Low-power clock distribution circuits for the Macro Pixel ASIC
title_sort low-power clock distribution circuits for the macro pixel asic
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/10/01/C01051
http://cds.cern.ch/record/2158930
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AT decaniof lowpowerclockdistributioncircuitsforthemacropixelasic
AT manghisonim lowpowerclockdistributioncircuitsforthemacropixelasic
AT rattil lowpowerclockdistributioncircuitsforthemacropixelasic
AT rev lowpowerclockdistributioncircuitsforthemacropixelasic
AT traversig lowpowerclockdistributioncircuitsforthemacropixelasic
AT marchioroa lowpowerclockdistributioncircuitsforthemacropixelasic
AT kloukinask lowpowerclockdistributioncircuitsforthemacropixelasic

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