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The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
A radiation-tolerant CDR/PLL ASIC has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR), showing deterministic phase and low jitter. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs...
| Autores principales: | , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2015
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/10/03/C03024 http://cds.cern.ch/record/2158964 |