A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip

This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock...

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Detalles Bibliográficos
Autores principales: Lattuca, A, Mazza, G, Rinella, G Aglieri, Cavicchioli, C, Chanlek, N, Collu, A, Degerli, Y, Dorokhov, A, Flouzat, C, Gajanana, D, Gao, C, Guilloux, F, Hillemanns, H, Hristozkov, S, Junique, A, Keil, M, Kim, D, Kofarago, M, Kugathasan, T, Kwon, Y, Mager, M, Sielewicz, K Marek, Marin Tobon, C Augusto, Marras, D, Martinengo, P, Mugnier, H, Musa, L, Pham, T Hung, Puggioni, C, Reidt, F, Riedler, P, Rousset, J, Siddhanta, S, Snoeys, W, Song, M, Usai, G, Van Hoorne, J Willem, Yang, P
Lenguaje:eng
Publicado: 2016
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/11/01/C01066
http://cds.cern.ch/record/2252362

Internet

https://dx.doi.org/10.1088/1748-0221/11/01/C01066
http://cds.cern.ch/record/2252362

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