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A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip
This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock...
| Autores principales: | , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2016
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/11/01/C01066 http://cds.cern.ch/record/2252362 |
| _version_ | 1780953539951984640 |
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| author | Lattuca, A Mazza, G Rinella, G Aglieri Cavicchioli, C Chanlek, N Collu, A Degerli, Y Dorokhov, A Flouzat, C Gajanana, D Gao, C Guilloux, F Hillemanns, H Hristozkov, S Junique, A Keil, M Kim, D Kofarago, M Kugathasan, T Kwon, Y Mager, M Sielewicz, K Marek Marin Tobon, C Augusto Marras, D Martinengo, P Mugnier, H Musa, L Pham, T Hung Puggioni, C Reidt, F Riedler, P Rousset, J Siddhanta, S Snoeys, W Song, M Usai, G Van Hoorne, J Willem Yang, P |
| author_facet | Lattuca, A Mazza, G Rinella, G Aglieri Cavicchioli, C Chanlek, N Collu, A Degerli, Y Dorokhov, A Flouzat, C Gajanana, D Gao, C Guilloux, F Hillemanns, H Hristozkov, S Junique, A Keil, M Kim, D Kofarago, M Kugathasan, T Kwon, Y Mager, M Sielewicz, K Marek Marin Tobon, C Augusto Marras, D Martinengo, P Mugnier, H Musa, L Pham, T Hung Puggioni, C Reidt, F Riedler, P Rousset, J Siddhanta, S Snoeys, W Song, M Usai, G Van Hoorne, J Willem Yang, P |
| author_sort | Lattuca, A |
| collection | CERN |
| description | This work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented. |
| id | oai-inspirehep.net-1418323 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2016 |
| record_format | invenio |
| spelling | oai-inspirehep.net-14183232022-08-10T12:49:18Zdoi:10.1088/1748-0221/11/01/C01066http://cds.cern.ch/record/2252362engLattuca, AMazza, GRinella, G AglieriCavicchioli, CChanlek, NCollu, ADegerli, YDorokhov, AFlouzat, CGajanana, DGao, CGuilloux, FHillemanns, HHristozkov, SJunique, AKeil, MKim, DKofarago, MKugathasan, TKwon, YMager, MSielewicz, K MarekMarin Tobon, C AugustoMarras, DMartinengo, PMugnier, HMusa, LPham, T HungPuggioni, CReidt, FRiedler, PRousset, JSiddhanta, SSnoeys, WSong, MUsai, GVan Hoorne, J WillemYang, PA CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chipDetectors and Experimental TechniquesThis work presents the 600 MHz clock multiplier PLL and the pseudo-LVDS driver which are two essential components of the Data Transmission Unit (DTU), a fast serial link for the 1.2 Gb/s data transmission of the ALICE inner detector front-end chip (ALPIDE). The PLL multiplies the 40 MHz input clock in order to obtain the 600 MHz and the 200 MHz clock for a fast serializer which works in Double Data Rate mode. The outputs of the serializer feed the pseudo-LVDS driver inputs which transmits the data from the pixel chip to the patch panel with a limited number of signal lines. The driver drives a 5.3 m-6.5 m long differential transmission line by steering a maximum of 5 mA of current at the target speed. To overcome bandwidth limitations coming from the long cables the pre-emphasis can be applied to the output. Currents for the main and pre-emphasis driver can individually be adjusted using on-chip digital-to-analog converters. The circuits will be integrated in the pixel chip and are designed in the same 0.18 μm CMOS technology and will operate from the same 1.8 V supply. Design and test results of both circuits are presented.oai:inspirehep.net:14183232016 |
| spellingShingle | Detectors and Experimental Techniques Lattuca, A Mazza, G Rinella, G Aglieri Cavicchioli, C Chanlek, N Collu, A Degerli, Y Dorokhov, A Flouzat, C Gajanana, D Gao, C Guilloux, F Hillemanns, H Hristozkov, S Junique, A Keil, M Kim, D Kofarago, M Kugathasan, T Kwon, Y Mager, M Sielewicz, K Marek Marin Tobon, C Augusto Marras, D Martinengo, P Mugnier, H Musa, L Pham, T Hung Puggioni, C Reidt, F Riedler, P Rousset, J Siddhanta, S Snoeys, W Song, M Usai, G Van Hoorne, J Willem Yang, P A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip |
| title | A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip |
| title_full | A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip |
| title_fullStr | A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip |
| title_full_unstemmed | A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip |
| title_short | A CMOS 0.18 μm 600 MHz clock multiplier PLL and a pseudo-LVDS driver for the high speed data transmission for the ALICE Inner Tracking System front-end chip |
| title_sort | cmos 0.18 μm 600 mhz clock multiplier pll and a pseudo-lvds driver for the high speed data transmission for the alice inner tracking system front-end chip |
| topic | Detectors and Experimental Techniques |
| url | https://dx.doi.org/10.1088/1748-0221/11/01/C01066 http://cds.cern.ch/record/2252362 |
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