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Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data
The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral...
| Autores principales: | , , , , |
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| Lenguaje: | eng |
| Publicado: |
2016
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/11/01/C01069 http://cds.cern.ch/record/2252363 |