Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue a...

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Detalles Bibliográficos
Autores principales: Degerli, Y, Godiot, S, Guilloux, F, Hemperek, T, Krüger, H, Lachkar, M, Liu, J, Orsini, F, Pangaud, P, Rymaszewski, P, Wang, T
Lenguaje:eng
Publicado: 2016
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/11/12/C12064
http://cds.cern.ch/record/2291317

Internet

https://dx.doi.org/10.1088/1748-0221/11/12/C12064
http://cds.cern.ch/record/2291317

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