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Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically dif...
| Autores principales: | , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2017
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/12/02/C02039 http://cds.cern.ch/record/2275135 |