Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically dif...

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Detalles Bibliográficos
Autores principales: Casas, L M Jara, Ceresa, D, Kulis, S, Miryala, S, Christiansen, J, Francisco, R, Gnani, D
Lenguaje:eng
Publicado: 2017
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/12/02/C02039
http://cds.cern.ch/record/2275135
_version_ 1780955149019119616
author Casas, L M Jara
Ceresa, D
Kulis, S
Miryala, S
Christiansen, J
Francisco, R
Gnani, D
author_facet Casas, L M Jara
Ceresa, D
Kulis, S
Miryala, S
Christiansen, J
Francisco, R
Gnani, D
author_sort Casas, L M Jara
collection CERN
description A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.
id oai-inspirehep.net-1513713
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2017
record_format invenio
spelling oai-inspirehep.net-15137132019-10-15T15:19:45Zdoi:10.1088/1748-0221/12/02/C02039http://cds.cern.ch/record/2275135engCasas, L M JaraCeresa, DKulis, SMiryala, SChristiansen, JFrancisco, RGnani, DCharacterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chipDetectors and Experimental TechniquesA Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically differing in the device dimensions, Vt flavor and layout of the device. Each library has eighteen test structures specifically designed to characterize delay degradation and power consumption of the standard cells. For SEU study, a dedicated test structure based on a shift register is designed for each library. TID results up to 500 Mrad are reported.oai:inspirehep.net:15137132017
spellingShingle Detectors and Experimental Techniques
Casas, L M Jara
Ceresa, D
Kulis, S
Miryala, S
Christiansen, J
Francisco, R
Gnani, D
Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
title Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
title_full Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
title_fullStr Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
title_full_unstemmed Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
title_short Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip
title_sort characterization of radiation effects in 65 nm digital circuits with the drad digital radiation test chip
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.1088/1748-0221/12/02/C02039
http://cds.cern.ch/record/2275135
work_keys_str_mv AT casaslmjara characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip
AT ceresad characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip
AT kuliss characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip
AT miryalas characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip
AT christiansenj characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip
AT franciscor characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip
AT gnanid characterizationofradiationeffectsin65nmdigitalcircuitswiththedraddigitalradiationtestchip

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