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Characterization of radiation effects in 65 nm digital circuits with the DRAD digital radiation test chip

A Digital RADiation (DRAD) test chip has been specifically designed to study the impact of Total Ionizing Dose (TID) (<1 Grad) and Single Event Upset (SEU) on digital logic gates in a 65 nm CMOS technology. Nine different versions of standard cell libraries are studied in this chip, basically dif...

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Detalles Bibliográficos
Autores principales:	Casas, L M Jara, Ceresa, D, Kulis, S, Miryala, S, Christiansen, J, Francisco, R, Gnani, D
Lenguaje:	eng
Publicado:	2017
Materias:	Detectors and Experimental Techniques
Acceso en línea:	https://dx.doi.org/10.1088/1748-0221/12/02/C02039 http://cds.cern.ch/record/2275135

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