A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC

This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at $3 GHz/cm^{2}$ pixel rate, trigger fre...

Descripción completa

Detalles Bibliográficos
Autores principales: Paternò, Andrea, Pacher, L, Monteil, E, Loddo, F, Demaria, N, Gaioni, L, Canio, F De, Traversi, G, Re, V, Ratti, L, Rivetti, A, Da Rocha Rolo, M, Dellacasa, G, Mazza, G, Marzocca, C, Licciulli, F, Ciciriello, F, Marconi, S, Placidi, P, Magazzù, G, Stabile, A, Mattiazzo, S, Veri, C
Lenguaje:eng
Publicado: 2017
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1088/1748-0221/12/02/C02043
http://cds.cern.ch/record/2275141

Internet

https://dx.doi.org/10.1088/1748-0221/12/02/C02043
http://cds.cern.ch/record/2275141

Ejemplares similares