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A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC
This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at $3 GHz/cm^{2}$ pixel rate, trigger fre...
| Autores principales: | , , , , , , , , , , , , , , , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2017
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1088/1748-0221/12/02/C02043 http://cds.cern.ch/record/2275141 |
| _version_ | 1780955150291042304 |
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| author | Paternò, Andrea Pacher, L Monteil, E Loddo, F Demaria, N Gaioni, L Canio, F De Traversi, G Re, V Ratti, L Rivetti, A Da Rocha Rolo, M Dellacasa, G Mazza, G Marzocca, C Licciulli, F Ciciriello, F Marconi, S Placidi, P Magazzù, G Stabile, A Mattiazzo, S Veri, C |
| author_facet | Paternò, Andrea Pacher, L Monteil, E Loddo, F Demaria, N Gaioni, L Canio, F De Traversi, G Re, V Ratti, L Rivetti, A Da Rocha Rolo, M Dellacasa, G Mazza, G Marzocca, C Licciulli, F Ciciriello, F Marconi, S Placidi, P Magazzù, G Stabile, A Mattiazzo, S Veri, C |
| author_sort | Paternò, Andrea |
| collection | CERN |
| description | This paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at $3 GHz/cm^{2}$ pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad. |
| id | oai-inspirehep.net-1513921 |
| institution | Organización Europea para la Investigación Nuclear |
| language | eng |
| publishDate | 2017 |
| record_format | invenio |
| spelling | oai-inspirehep.net-15139212019-10-15T15:18:12Zdoi:10.1088/1748-0221/12/02/C02043http://cds.cern.ch/record/2275141engPaternò, AndreaPacher, LMonteil, ELoddo, FDemaria, NGaioni, LCanio, F DeTraversi, GRe, VRatti, LRivetti, ADa Rocha Rolo, MDellacasa, GMazza, GMarzocca, CLicciulli, FCiciriello, FMarconi, SPlacidi, PMagazzù, GStabile, AMattiazzo, SVeri, CA prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHCDetectors and Experimental TechniquesThis paper describes a readout ASIC prototype designed by the CHIPIX65 project, part of RD53, for a pixel detector at HL-LHC . A 64×64 matrix of $50×50μm^{2}$ pixels is realised. A digital architecture has been developed, with particle efficiency above 99.5% at $3 GHz/cm^{2}$ pixel rate, trigger frequency of 1 MHz and 12.5μsec latency. Two analog front end designs, one synchronous and one asynchronous, are implemented. Charge is measured with 5-bit precision, analog dead-time below 1%. The chip integrates for the first time many of the components developed by the collaboration in the past, including the Digital-to-Analog converters, Bandgap reference, Serializer, sLVS drivers, and analog Front Ends. Irradiation tests on these components proved their reliability up to 600 Mrad.oai:inspirehep.net:15139212017 |
| spellingShingle | Detectors and Experimental Techniques Paternò, Andrea Pacher, L Monteil, E Loddo, F Demaria, N Gaioni, L Canio, F De Traversi, G Re, V Ratti, L Rivetti, A Da Rocha Rolo, M Dellacasa, G Mazza, G Marzocca, C Licciulli, F Ciciriello, F Marconi, S Placidi, P Magazzù, G Stabile, A Mattiazzo, S Veri, C A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC |
| title | A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC |
| title_full | A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC |
| title_fullStr | A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC |
| title_full_unstemmed | A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC |
| title_short | A prototype of pixel readout ASIC in 65 nm CMOS technology for extreme hit rate detectors at HL-LHC |
| title_sort | prototype of pixel readout asic in 65 nm cmos technology for extreme hit rate detectors at hl-lhc |
| topic | Detectors and Experimental Techniques |
| url | https://dx.doi.org/10.1088/1748-0221/12/02/C02043 http://cds.cern.ch/record/2275141 |
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