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A testbench research based on UVM for ABCStar
As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constru...
| Autores principales: | , , , , , |
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| Lenguaje: | eng |
| Publicado: |
2016
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.1109/RTC.2016.7543181 http://cds.cern.ch/record/2263755 |