A testbench research based on UVM for ABCStar

As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constru...

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Detalles Bibliográficos
Autores principales: Cheng, Li-Bo, Anghinolfi, Francis, Wang, Ke, Zhu, Hong-Bo, Lu, Wei-Guo, Liu, Zhen-An
Lenguaje:eng
Publicado: 2016
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.1109/RTC.2016.7543181
http://cds.cern.ch/record/2263755
Descripción
Sumario:As physicists want to put more and more functionalities and algorithms into frontend ASICs, the logic design (of some ASICs) become more and more complicated. A reliable, robust functional verification testbench is one of the most important part during ASIC design. This paper presents a well-constructed testbench based on Universal Verification Methodology(UVM) research for ATLAS Phase-II upgrade silicon strip detector front-end readout chip.

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