Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage co...

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Detalles Bibliográficos
Autores principales: Gaioni, L, Braga, D, Christian, D, Deptuch, G, Fahim , F, Nodari, B, Ratti, L, Re, V, Zimmerman, T
Lenguaje:eng
Publicado: SISSA 2018
Materias:
Detectors and Experimental Techniques
Acceso en línea:https://dx.doi.org/10.22323/1.313.0021
http://cds.cern.ch/record/2673782
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author Gaioni, L
Braga, D
Christian, D
Deptuch, G
Fahim , F
Nodari, B
Ratti, L
Re, V
Zimmerman, T
author_facet Gaioni, L
Braga, D
Christian, D
Deptuch, G
Fahim , F
Nodari, B
Ratti, L
Re, V
Zimmerman, T
author_sort Gaioni, L
collection CERN
description This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided.
id oai-inspirehep.net-1644036
institution Organización Europea para la Investigación Nuclear
language eng
publishDate 2018
publisher SISSA
record_format invenio
spelling oai-inspirehep.net-16440362021-05-03T07:54:00Zdoi:10.22323/1.313.0021http://cds.cern.ch/record/2673782engGaioni, LBraga, DChristian, DDeptuch, GFahim , FNodari, BRatti, LRe, VZimmerman, TDesign and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel DetectorsDetectors and Experimental TechniquesThis work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided.SISSAFERMILAB-CONF-17-461-PPDoai:inspirehep.net:16440362018
spellingShingle Detectors and Experimental Techniques
Gaioni, L
Braga, D
Christian, D
Deptuch, G
Fahim , F
Nodari, B
Ratti, L
Re, V
Zimmerman, T
Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
title Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
title_full Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
title_fullStr Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
title_full_unstemmed Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
title_short Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
title_sort design and test of a 65nm cmos front-end with zero dead time for next generation pixel detectors
topic Detectors and Experimental Techniques
url https://dx.doi.org/10.22323/1.313.0021
http://cds.cern.ch/record/2673782
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