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Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors
This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage co...
| Autores principales: | , , , , , , , , |
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| Lenguaje: | eng |
| Publicado: |
SISSA
2018
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| Materias: | |
| Acceso en línea: | https://dx.doi.org/10.22323/1.313.0021 http://cds.cern.ch/record/2673782 |