Substrate-currents-aware characterization of an integrated buck DC/DC converter for floor-plan optimization

The performance of integrated DC/DC converters is affected by substrate parasitic devices, such as bipolar transistors and thyristors: these devices cause enhanced substrate noise that can lead to the malfunctioning of the control circuitry, they degrade the efficiency, and thyristors can even cause the failure of the converter by latch-up. Due to the lack of software tools for the evaluation of the effects of such parasitic devices in the design phase, often only qualitative counter-measures are taken. This can lead to sub-optimal floor-plans in terms of substrate noise immunity of the control circuitry, power efficiency and area consumption. Being the effects of the substrate parasitic devices often overlooked in the characterization phase, in this work we propose a systematic approach to evaluate such effects in a buck converter. Such method can be used to determine the best floor-plan among several options. Finally, we apply the method to compare two different floor-plans of an integrated buck converter designed in a 130 nm technology.