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Design of memory subsystem for wide input data range in the SALT ASIC
The paper presents the design and optimisation of memory buffer in the SALT (Silicon ASIC for LHCb Tracking) ASIC. The SALT is a new 128-channel readout ASIC for silicon strip detectors in the Large Hadron Collider beauty (LHCb) experiment at the Large Hadron Collider (LHC) in CERN. The stochastic n...
| Autores principales: | , |
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| Lenguaje: | eng |
| Publicado: |
2017
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| Acceso en línea: | https://dx.doi.org/10.23919/MIXDES.2017.8005192 http://cds.cern.ch/record/2310548 |